Applicant's co-pending U.S. patent application Ser. No. 13/159,871, filed Jun. 14, 2011 teaches techniques for distributing a high-bandwidth analog signal to the front end of a multipath analog to digital converter. FIGS. 1A and 1B illustrate principle elements of a receiver module in accordance with U.S. patent application Ser. No. 13/159,871.
Referring to FIG. 1A, the receiver module 2 comprises an electro-optic IC 4 coupled to an electronic signal processor IC 6 via a parallel analog transmission line bus 8. The electro-optic IC 4 includes a 90° optical hybrid 10, a photodetector block 12, and an analog frequency decimation block 14. The optical hybrid 10 receives an incoming optical channel light and a local oscillator light through respective pigtails 16 and 18, and operates in a conventional manner to mix the two lights together to generate composite lights that are made incident on the photodetector block 12. Similarly, the photodetector block 12 operates in a conventional manner to generate an analog photodetector signal V that is proportional to the power of the incident composite light. The frequency decimation block 14 processes the photodetector signal to yield a set of parallel analog signals Vx (where x is an index value, x=1 . . . N) which, when taken together, contain all of the information content modulated on the photodetector signal V; but which, taken individually, have a lower bandwidth than the photodetector current V. The electronic signal processor IC 6 comprises analog signal conditioning circuits (such as power amplifiers, filters etc., not shown) and analog-to-digital (A/D) converters 20 for converting the analog electrical signals Vx from the frequency decimation block 14 into raw digital sample streams which are processed by the DSP 22 to reconstruct the spectrum of the photodetector signal V and recover digital data signals modulated on the received optical channel signal
As is known in the art, a conventional 90° optical hybrid is configured to mix the received optical channel light with the LO light and a 90° phase-shifted version of the LO light, to generate corresponding In-Phase and Quadrature composite lights for each of two polarizations of the incoming optical channel light. In many practical embodiments, it is desirable to provide respective parallel signal paths (each comprising a photodetector 12 and an analog frequency decimation block 14) for receiving and processing each of these composite lights. However, for simplicity of illustration, only the In-Phase signal path for a single polarization is shown in FIG. 1A, it being understood that the signal path(s) for the corresponding Quadrature composite light, and for the second polarization (if any), could be provided by suitably duplicating the elements of the In-Phase signal path.
Referring to FIG. 1B, a representative frequency decimation block 14 comprises an analog 1:N power splitter 24, which receives the photodetector current V, and outputs a set of N parallel duplicates of the photodetector current V in a known manner. In the illustrated embodiment, N=4, but this is not essential. Increasing the number N of outputs reduces the bandwidth performance requirements of the analog transmission line bus 8, at the cost of increased complexity. For enhanced performance the splitter 24 may contain filtering and or preamplification functions which, for simplicity of illustration, are not shown in the drawings. Each output of the 1:N splitter 24 is connected to a respective analog signal path, each of which includes a respective non-linear processor 26a-d cascaded with a low-pass filter (LPF) 28a-d. Each non-linear processor 26 applies a non-linear operation to the photodetector current V using a respective branch signal Bx to yield a composite signal VBx that is supplied the LPF 28. The LPF 28 operates in a conventional manner to attenuate undesired high-frequency components to yield a low bandwidth analog signal Vx, which can be transmitted through the analog transmission line bus 8 to the electronic signal processing IC 6.
The non-linear processor 26 can be designed to implement any suitable non-linear operation. For example, in the embodiment of FIGS. 1A-1B, the non-linear processor 26 is implemented as a conventional Radio Frequency (RF) mixer, which operates to combine the photodetector current V and the respective branch signal Bx in a known manner. In an embodiment in which the branch signals Bx are continuous wave sinusoidal signals, the non-linear function is the well known heterodyne or homodyne function. In embodiments in which the branch signals Bx are binary digital signals, the non-linear function approximates a switching or sampling function, depending on the duty cycle of the branch signals Bx.
In the embodiment of FIGS. 1A-1B the N signal paths are supplied (driven) with a copy of the input signal V output from the power splitter 24 which, in practical implementations, will normally include a preamplifier stage (not shown). A typical preamplifier stage has undesirable characteristics, such as some combination of bandwidth limitation, excessive power consumption and excessive distortion, which are substantially aggravated by the requirement to drive multiple signal paths. The fundamental limitation is known to be one of gain-bandwidth product. For example, for a given preamplifier stage it is necessary to trade off bandwidth against power gain, and if, for example, two preamplifier stages are connected in series and need to be driven with a certain power level, then the bandwidth available will be reduced by a factor of approximately two.
It is known, for Walsh and frequency-domain architectures such as those illustrated in FIGS. 1A and 1B, to use a tree structure so that the number of preamplifier stages that must be driven can be reduced to as few as two, or often four.
It may appear that, in a time-interleaved system, it is only necessary for the preamplifier/power splitter 24 to drive one sampler (A/D converter) 20 at any given time, but in practice two design requirements combine to make the drive requirement equal to that for all N samplers 20 at once. One such design requirement is for sufficiently fast settling, in that each sampler 20 must settle completely at the full sample rate of the system, rather than that of an individual signal path. Another requirement is for moderate duty cycles in switch-control waveforms, which may cause the designer to have several samplers 20 tracking and hence loading the preamplifier at any given time.
In Walsh and frequency-domain architectures in which all channels (signal paths) are driven directly, it is also known that at least some of the signal power supplied to the input of each channel will be rejected. For many practical classes of input signal, it is known that this unnecessary signal power adds distortion and increases requirements for power consumption in the individual channels.
These two design constraints pose problems because both run counter to the desire for high-speed performance.
Techniques that overcome limitations of the prior art remain highly desirable.